1. Field of the Invention
The present invention relates generally to integrated circuits semiconductor memories, and more specifically to a read write memory in which a load circuit is provided for each array of memory cells as a load of the transistors of each memory cell.
2. Description of the Related Art
In a prior art static random access memory where each memory cell is supplied with a voltage through a bit line from a circuit that serves as a load of the driving transistors of the cell through a gate-controlled coupling transistor, a voltage developed at the bit line is determined by the ratio of the ON-resistance value of the loading transistor to the combined ON-resistance values of the coupling transistor and one of the driving transistors of the cell. Since the operating characteristics of these transistors vary with device variabilities due to manufacture and temperature variations, the memory is designed with a safety margin to accommodate such factors, and hence, the operating performance of the memory cannot be exploited to the fullest extent.